URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_22] - Rev 1152

Rev	Log message	Author	Age	Path
1132	RFRAM defines comments updated. Altera LPM option added.	lampret	7767d 23h	/or1k/tags/rel_22
1131	Added another pipe stage to match gmult. One day second pipe in amult and gmult might be removed to get better performance.	lampret	7767d 23h	/or1k/tags/rel_22
1130	RFRAM type always need to be defined.	lampret	7767d 23h	/or1k/tags/rel_22
1129	Added Altera LPM RAMs. Changed generic RAM output when OE inactive.	lampret	7767d 23h	/or1k/tags/rel_22
1128	Fixed my bustage: Add missing 2nd argument to open(). Otherwise, opening a serial port channel can sporadically fail.	sfurman	7772d 22h	/or1k/tags/rel_22
1127	Added ability to map I/O from simulated UARTs to physical serial ports on the host running the simulator.	sfurman	7775d 23h	/or1k/tags/rel_22
1126	Added lengthy comment explaining all possible choices for UART channels, e.g. xterm, tcp, file, etc.	sfurman	7778d 01h	/or1k/tags/rel_22
1125	This test case passes.	lampret	7789d 05h	/or1k/tags/rel_22
1124	Initialize or1k_implementation with reasonable defaults for the number of implementation registers. This doesn't affect the jtag or sim targets at all because those values are always overwritten when or1k_implementation is initialized. However, it is necessary when connecting to remote gdb stubs through a serial port or socket, since or1k_implementation is not yet initialized for those targets.	sfurman	7798d 20h	/or1k/tags/rel_22
1123	Renumber/rename SPRs to match latest architecture doc	sfurman	7800d 03h	/or1k/tags/rel_22