URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_24/] [or1200] - Rev 788

Rev	Log message	Author	Age	Path
571	Changed alignment exception EPCR. Not tested yet.	lampret	8216d 07h	/or1k/tags/rel_24/or1200
570	Fixed order of syscall and range exceptions.	lampret	8216d 09h	/or1k/tags/rel_24/or1200
569	Default ASIC configuration does not sample WB inputs.	lampret	8216d 19h	/or1k/tags/rel_24/or1200
562	Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.	lampret	8216d 22h	/or1k/tags/rel_24/or1200
536	Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be.	lampret	8223d 04h	/or1k/tags/rel_24/or1200
512	Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target.	lampret	8227d 07h	/or1k/tags/rel_24/or1200
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8227d 20h	/or1k/tags/rel_24/or1200
402	Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32	lampret	8258d 00h	/or1k/tags/rel_24/or1200
401	* empty log message *	simons	8261d 10h	/or1k/tags/rel_24/or1200
400	force_dslot_fetch does not work - allways zero.	simons	8261d 10h	/or1k/tags/rel_24/or1200