URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_25/] [or1200/] [rtl/] [verilog] - Rev 1022

Rev	Log message	Author	Age	Path
788	Some of the warnings fixed.	lampret	8142d 09h	/or1k/tags/rel_25/or1200/rtl/verilog
778	Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.	lampret	8143d 05h	/or1k/tags/rel_25/or1200/rtl/verilog
777	Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2	lampret	8143d 05h	/or1k/tags/rel_25/or1200/rtl/verilog
776	Updated defines.	lampret	8143d 05h	/or1k/tags/rel_25/or1200/rtl/verilog
775	Optimized cache controller FSM.	lampret	8143d 05h	/or1k/tags/rel_25/or1200/rtl/verilog
774	Removed old files.	lampret	8143d 06h	/or1k/tags/rel_25/or1200/rtl/verilog
737	Added alternative for critical path in DU.	lampret	8158d 00h	/or1k/tags/rel_25/or1200/rtl/verilog
736	Changed generation of SPR address. Now it is ORed from base and offset instead of a sum.	lampret	8160d 23h	/or1k/tags/rel_25/or1200/rtl/verilog
735	Fixed async loop. Changed multiplier type for ASIC.	lampret	8160d 23h	/or1k/tags/rel_25/or1200/rtl/verilog
668	Lapsus fixed.	simons	8185d 09h	/or1k/tags/rel_25/or1200/rtl/verilog