URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_25/] [or1200/] [rtl/] [verilog] - Rev 1069

Rev	Log message	Author	Age	Path
942	Delayed external access at page crossing.	lampret	8006d 18h	/or1k/tags/rel_25/or1200/rtl/verilog
916	MAC now follows software convention (signed multiply instead of unsigned).	lampret	8018d 22h	/or1k/tags/rel_25/or1200/rtl/verilog
895	Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.	lampret	8035d 02h	/or1k/tags/rel_25/or1200/rtl/verilog
871	Generic flip-flop based memory macro for register file.	lampret	8071d 07h	/or1k/tags/rel_25/or1200/rtl/verilog
870	Added defines for enabling generic FF based memory macro for register file.	lampret	8071d 07h	/or1k/tags/rel_25/or1200/rtl/verilog
869	Added generic flip-flop based memory macro instantiation.	lampret	8071d 08h	/or1k/tags/rel_25/or1200/rtl/verilog
795	Added a directive to ignore signed division variables that are only used in simulation.	lampret	8142d 07h	/or1k/tags/rel_25/or1200/rtl/verilog
794	Added again just recently removed full_case directive	lampret	8142d 07h	/or1k/tags/rel_25/or1200/rtl/verilog
791	Fixed some ports in instnatiations that were removed from the modules	lampret	8142d 07h	/or1k/tags/rel_25/or1200/rtl/verilog
790	Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives	lampret	8142d 07h	/or1k/tags/rel_25/or1200/rtl/verilog