URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_25/] [or1200/] [rtl/] [verilog] - Rev 1210

Rev	Log message	Author	Age	Path
1079	RAMs wrong connected to the BIST scan chain.	mohor	7929d 00h	/or1k/tags/rel_25/or1200/rtl/verilog
1078	Previous check-in was done by mistake.	mohor	7929d 01h	/or1k/tags/rel_25/or1200/rtl/verilog
1077	Signal scanb_sen renamed to scanb_en.	mohor	7929d 01h	/or1k/tags/rel_25/or1200/rtl/verilog
1069	Signal scanb_eni renamed to scanb_en	mohor	7932d 18h	/or1k/tags/rel_25/or1200/rtl/verilog
1063	Added BIST scan. Special VS RAMs need to be used to implement BIST.	lampret	7939d 20h	/or1k/tags/rel_25/or1200/rtl/verilog
1055	Removed obsolete comment.	lampret	7971d 13h	/or1k/tags/rel_25/or1200/rtl/verilog
1054	Fixed a combinational loop.	lampret	7971d 13h	/or1k/tags/rel_25/or1200/rtl/verilog
1053	Disabled cache inhibit atttribute.	lampret	7971d 13h	/or1k/tags/rel_25/or1200/rtl/verilog
1038	Fixed a typo, reported by Taylor Su.	lampret	7978d 21h	/or1k/tags/rel_25/or1200/rtl/verilog
1035	Added optional l.div/l.divu insns. By default they are disabled.	lampret	7979d 10h	/or1k/tags/rel_25/or1200/rtl/verilog