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[/] [or1k/] [tags/] [rel_25/] [or1200/] [rtl/] [verilog] - Rev 668

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Rev Log message Author Age Path
400 force_dslot_fetch does not work - allways zero. simons 8290d 11h /or1k/tags/rel_25/or1200/rtl/verilog
399 Trap insn couses break after exits ex_insn. simons 8290d 11h /or1k/tags/rel_25/or1200/rtl/verilog
391 Fixed except_stop width and fixed EX PC for 1400444f no-ops. lampret 8293d 07h /or1k/tags/rel_25/or1200/rtl/verilog
390 Changed instantiation name of VS RAMs. lampret 8293d 08h /or1k/tags/rel_25/or1200/rtl/verilog
387 Now FPGA and ASIC target are separate. lampret 8293d 10h /or1k/tags/rel_25/or1200/rtl/verilog
386 Fixed VS RAM instantiation - again. lampret 8293d 10h /or1k/tags/rel_25/or1200/rtl/verilog
370 Program counter divided to PPC and NPC. simons 8297d 08h /or1k/tags/rel_25/or1200/rtl/verilog
367 Changed DSR/DRR behavior and exception detection. lampret 8297d 21h /or1k/tags/rel_25/or1200/rtl/verilog
365 Added wb_cyc_o assignment after it was removed by accident. lampret 8298d 16h /or1k/tags/rel_25/or1200/rtl/verilog
360 Added OR1200_REGISTERED_INPUTS. lampret 8300d 08h /or1k/tags/rel_25/or1200/rtl/verilog

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