URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_25/] [or1200/] [rtl/] [verilog] - Rev 791

Rev	Log message	Author	Age	Path
589	No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.	lampret	8212d 22h	/or1k/tags/rel_25/or1200/rtl/verilog
573	Fixed module name when compiling with OR1200_XILINX_RAM32X1D	lampret	8216d 00h	/or1k/tags/rel_25/or1200/rtl/verilog
571	Changed alignment exception EPCR. Not tested yet.	lampret	8216d 09h	/or1k/tags/rel_25/or1200/rtl/verilog
570	Fixed order of syscall and range exceptions.	lampret	8216d 11h	/or1k/tags/rel_25/or1200/rtl/verilog
569	Default ASIC configuration does not sample WB inputs.	lampret	8216d 20h	/or1k/tags/rel_25/or1200/rtl/verilog
562	Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.	lampret	8217d 00h	/or1k/tags/rel_25/or1200/rtl/verilog
536	Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be.	lampret	8223d 05h	/or1k/tags/rel_25/or1200/rtl/verilog
512	Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target.	lampret	8227d 09h	/or1k/tags/rel_25/or1200/rtl/verilog
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8227d 22h	/or1k/tags/rel_25/or1200/rtl/verilog
402	Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32	lampret	8258d 01h	/or1k/tags/rel_25/or1200/rtl/verilog