URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_25/] [or1200/] [rtl/] [verilog] - Rev 944

Rev	Log message	Author	Age	Path
735	Fixed async loop. Changed multiplier type for ASIC.	lampret	8161d 03h	/or1k/tags/rel_25/or1200/rtl/verilog
668	Lapsus fixed.	simons	8185d 13h	/or1k/tags/rel_25/or1200/rtl/verilog
663	No longer using async rst as sync reset for the counter.	lampret	8188d 03h	/or1k/tags/rel_25/or1200/rtl/verilog
660	Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.	lampret	8189d 00h	/or1k/tags/rel_25/or1200/rtl/verilog
636	Fixed combinational loops.	lampret	8198d 09h	/or1k/tags/rel_25/or1200/rtl/verilog
617	Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.	lampret	8203d 03h	/or1k/tags/rel_25/or1200/rtl/verilog
610	Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.	lampret	8207d 21h	/or1k/tags/rel_25/or1200/rtl/verilog
597	Fixed OR1200_XILINX_RAM32X1D.	lampret	8211d 14h	/or1k/tags/rel_25/or1200/rtl/verilog
596	SR[TEE] should be zero after reset.	lampret	8211d 19h	/or1k/tags/rel_25/or1200/rtl/verilog
595	Fixed 'the NPC single-step fix'.	lampret	8212d 14h	/or1k/tags/rel_25/or1200/rtl/verilog