OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_25/] [or1200/] [rtl] - Rev 1023

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8173d 04h /or1k/tags/rel_25/or1200/rtl
788 Some of the warnings fixed. lampret 8173d 06h /or1k/tags/rel_25/or1200/rtl
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8174d 01h /or1k/tags/rel_25/or1200/rtl
777 Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2 lampret 8174d 02h /or1k/tags/rel_25/or1200/rtl
776 Updated defines. lampret 8174d 02h /or1k/tags/rel_25/or1200/rtl
775 Optimized cache controller FSM. lampret 8174d 02h /or1k/tags/rel_25/or1200/rtl
774 Removed old files. lampret 8174d 02h /or1k/tags/rel_25/or1200/rtl
737 Added alternative for critical path in DU. lampret 8188d 20h /or1k/tags/rel_25/or1200/rtl
736 Changed generation of SPR address. Now it is ORed from base and offset instead of a sum. lampret 8191d 19h /or1k/tags/rel_25/or1200/rtl
735 Fixed async loop. Changed multiplier type for ASIC. lampret 8191d 19h /or1k/tags/rel_25/or1200/rtl

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.