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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Rev 1063

Rev	Log message	Author	Age	Path
660	Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.	lampret	8184d 00h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
636	Fixed combinational loops.	lampret	8193d 09h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
597	Fixed OR1200_XILINX_RAM32X1D.	lampret	8206d 15h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
589	No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.	lampret	8207d 21h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
569	Default ASIC configuration does not sample WB inputs.	lampret	8211d 19h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
536	Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be.	lampret	8218d 04h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
512	Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target.	lampret	8222d 08h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8222d 21h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v