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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Rev 1139

Rev	Log message	Author	Age	Path
788	Some of the warnings fixed.	lampret	8137d 13h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
778	Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.	lampret	8138d 08h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
776	Updated defines.	lampret	8138d 09h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
737	Added alternative for critical path in DU.	lampret	8153d 03h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
735	Fixed async loop. Changed multiplier type for ASIC.	lampret	8156d 02h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
660	Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.	lampret	8183d 23h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
636	Fixed combinational loops.	lampret	8193d 08h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
597	Fixed OR1200_XILINX_RAM32X1D.	lampret	8206d 14h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
589	No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.	lampret	8207d 20h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
569	Default ASIC configuration does not sample WB inputs.	lampret	8211d 18h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v