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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Rev 1225

Rev	Log message	Author	Age	Path
984	Disable SB until it is tested	lampret	8019d 05h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
977	Added store buffer.	lampret	8019d 07h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
962	Fixed Xilinx trace buffer address. REported by Taylor Su.	lampret	8022d 21h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
944	Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.	lampret	8025d 22h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
895	Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.	lampret	8054d 05h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
870	Added defines for enabling generic FF based memory macro for register file.	lampret	8090d 11h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
790	Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives	lampret	8161d 11h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
788	Some of the warnings fixed.	lampret	8161d 12h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
778	Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.	lampret	8162d 08h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
776	Updated defines.	lampret	8162d 08h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v