OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Rev 1226

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 7999d 19h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
984 Disable SB until it is tested lampret 8002d 23h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
977 Added store buffer. lampret 8003d 01h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 8006d 15h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
944 Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. lampret 8009d 16h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8037d 23h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
870 Added defines for enabling generic FF based memory macro for register file. lampret 8074d 05h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8145d 05h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
788 Some of the warnings fixed. lampret 8145d 06h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8146d 02h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.