URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_7] - Rev 819

Rev	Log message	Author	Age	Path
797	Changed hardcoded address for fake MC to use a define.	lampret	8143d 12h	/or1k/tags/rel_7
796	Removed unused ports wb_clki and wb_rst_i	lampret	8143d 12h	/or1k/tags/rel_7
795	Added a directive to ignore signed division variables that are only used in simulation.	lampret	8143d 17h	/or1k/tags/rel_7
794	Added again just recently removed full_case directive	lampret	8143d 17h	/or1k/tags/rel_7
793	Added synthesis off/on for timescale.v included file.	lampret	8143d 17h	/or1k/tags/rel_7
792	Fixed port names that changed.	lampret	8143d 17h	/or1k/tags/rel_7
791	Fixed some ports in instnatiations that were removed from the modules	lampret	8143d 17h	/or1k/tags/rel_7
790	Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives	lampret	8143d 17h	/or1k/tags/rel_7
789	Added response from memory controller (addr 0x60000000)	lampret	8143d 18h	/or1k/tags/rel_7
788	Some of the warnings fixed.	lampret	8143d 18h	/or1k/tags/rel_7