URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_9/] - Rev 822

Rev	Log message	Author	Age	Path
800	Bug fixed.	simons	8140d 00h	/or1k/tags/rel_9
799	Wrapping around 512k boundary to simulate real hw.	simons	8143d 17h	/or1k/tags/rel_9
798	Hardware scroll added. This possible due to the fact that crt is wrapping around 512k boundary.	simons	8143d 17h	/or1k/tags/rel_9
797	Changed hardcoded address for fake MC to use a define.	lampret	8143d 18h	/or1k/tags/rel_9
796	Removed unused ports wb_clki and wb_rst_i	lampret	8143d 18h	/or1k/tags/rel_9
795	Added a directive to ignore signed division variables that are only used in simulation.	lampret	8143d 22h	/or1k/tags/rel_9
794	Added again just recently removed full_case directive	lampret	8143d 23h	/or1k/tags/rel_9
793	Added synthesis off/on for timescale.v included file.	lampret	8143d 23h	/or1k/tags/rel_9
792	Fixed port names that changed.	lampret	8143d 23h	/or1k/tags/rel_9
791	Fixed some ports in instnatiations that were removed from the modules	lampret	8143d 23h	/or1k/tags/rel_9