OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_1_0] - Rev 103

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
83 Updates. lampret 8504d 14h /or1k/tags/stable_0_1_0
82 Changed pctemp to pcnext. lampret 8504d 14h /or1k/tags/stable_0_1_0
80 First import. lampret 8532d 09h /or1k/tags/stable_0_1_0
79 Data and instruction cache simulation added. lampret 8534d 06h /or1k/tags/stable_0_1_0
78 (i/d)tlb_status lampret 8657d 20h /or1k/tags/stable_0_1_0
77 Regular update. lampret 8657d 20h /or1k/tags/stable_0_1_0
76 regular update lampret 8657d 20h /or1k/tags/stable_0_1_0
75 simgetstr added. eval_mem32 replaced with evalsim_mem32. lampret 8657d 20h /or1k/tags/stable_0_1_0
74 Same as DMMU. lampret 8664d 20h /or1k/tags/stable_0_1_0
73 Fixed all bugs. Now more or less works. IMMU still has some problems (exception start). lampret 8664d 20h /or1k/tags/stable_0_1_0

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.