URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0/] [or1ksim] - Rev 519

Rev	Log message	Author	Age	Path
492	uart THRE interrupt immedialty after write to IER	markom	8242d 23h	/or1k/tags/stable_0_2_0/or1ksim
491	pc command fixed	markom	8243d 19h	/or1k/tags/stable_0_2_0/or1ksim
490	clkcycle parsing problem fixed	markom	8243d 19h	/or1k/tags/stable_0_2_0/or1ksim
486	Updated documentation in default sim.cfg	erez	8244d 00h	/or1k/tags/stable_0_2_0/or1ksim
485	gdb.h moved to debug dir; except.ld renamed to default.ld	markom	8244d 02h	/or1k/tags/stable_0_2_0/or1ksim
484	Changed to support execution from various addresses.	simons	8244d 14h	/or1k/tags/stable_0_2_0/or1ksim
483	Implemented some GPIO tests	erez	8244d 15h	/or1k/tags/stable_0_2_0/or1ksim
482	profiling uses l.jr instead of obsolete l.jalr	markom	8244d 18h	/or1k/tags/stable_0_2_0/or1ksim
481	-f bug fixed	markom	8244d 19h	/or1k/tags/stable_0_2_0/or1ksim
480	RTL_SIM define added for shorter simulation runtime.	simons	8244d 19h	/or1k/tags/stable_0_2_0/or1ksim