URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc1] - Rev 96

Rev	Log message	Author	Age	Path
75	simgetstr added. eval_mem32 replaced with evalsim_mem32.	lampret	8685d 23h	/or1k/tags/stable_0_2_0_rc1
74	Same as DMMU.	lampret	8692d 22h	/or1k/tags/stable_0_2_0_rc1
73	Fixed all bugs. Now more or less works. IMMU still has some problems (exception start).	lampret	8692d 22h	/or1k/tags/stable_0_2_0_rc1
72	Added 'how to build GNU tools'	lampret	8697d 23h	/or1k/tags/stable_0_2_0_rc1
71	Clean two typos.	lampret	8703d 01h	/or1k/tags/stable_0_2_0_rc1
70	Basic setjmp/longjmp are ready.	lampret	8703d 01h	/or1k/tags/stable_0_2_0_rc1
69	Sim debug.	lampret	8704d 23h	/or1k/tags/stable_0_2_0_rc1
68	Added hook for l.sys 204. Changed SPR of flag (no more CCR)	lampret	8704d 23h	/or1k/tags/stable_0_2_0_rc1
67	Added simulator "application load".	lampret	8704d 23h	/or1k/tags/stable_0_2_0_rc1
66	Added another set of eval_ functions that should be used directly by simulator. evalsim_ and setsim_ don't go through MMU transaltion mechanism.	lampret	8704d 23h	/or1k/tags/stable_0_2_0_rc1