OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [insight] - Rev 578

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
262 small bug in build_automata fixed; configure for memory markom 8290d 17h /or1k/tags/stable_0_2_0_rc2/insight
221 major changes to testbench; debug unit is moved to /debug; memory organization can be customized; UART from simons; overall cleanup markom 8299d 18h /or1k/tags/stable_0_2_0_rc2/insight
207 Several major changes to allow gdb to work with an Or1k implementation
that does not need a writeable PC. This version will use the breakpoint
vector and install a new vector into the EPC register, and then single
step out of the breakpoint exception. The breakpoint exception vector
must include only 2 commands: l.rfe and l.nop. Anything else and this
gdb version will fail w/ or1ksim.
chris 8326d 21h /or1k/tags/stable_0_2_0_rc2/insight
174 Few changes that should be done previously:
- machine.h replaced by spr_defs.h
- if reset label does not exist, boot from 0x0100
markom 8368d 19h /or1k/tags/stable_0_2_0_rc2/insight
151 Typo in the previous commit. Sorry. chris 8418d 22h /or1k/tags/stable_0_2_0_rc2/insight
150 Fixed some single stepping issues chris 8418d 22h /or1k/tags/stable_0_2_0_rc2/insight
149 Fixed bug where disassemble command caused a segmentation fault chris 8420d 01h /or1k/tags/stable_0_2_0_rc2/insight
146 Mofications to work with or1ksim JTAG based simulation chris 8420d 17h /or1k/tags/stable_0_2_0_rc2/insight
144 Modifications necessary for functional gdb interface chris 8420d 17h /or1k/tags/stable_0_2_0_rc2/insight
143 Modifications necessary to work with JTAG or1ksim simulator chris 8420d 17h /or1k/tags/stable_0_2_0_rc2/insight

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.