URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [or1ksim/] [cache/] - Rev 1765

Rev	Log message	Author	Age	Path
1099	cvs bug fixed	markom	7927d 07h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache
1085	Bug fixed.	simons	7939d 21h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache
997	PRINTF should be used instead of printf; command redirection repaired	markom	8029d 10h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache
992	A bug when cache enabled and bus error comes fixed.	simons	8031d 02h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache
970	Testbench is now running on ORP architecture platform.	simons	8036d 21h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache
884	code cleaning - a lot of global variables moved to runtime struct	markom	8073d 08h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache
876	Beta release of ATA simulation	rherveille	8080d 20h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache
638	TLBTR CI bit is now working properly.	simons	8231d 22h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache
631	Real cache access is simulated now.	simons	8234d 21h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache
626	store buffer added	markom	8235d 10h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache