URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc2] - Rev 215

Rev	Log message	Author	Age	Path
195	New test added.	simons	8346d 08h	/or1k/tags/stable_0_2_0_rc2
194	Fixed a bug for little endian architectures. Could cause a hang of gdb under some circumstances.	chris	8346d 16h	/or1k/tags/stable_0_2_0_rc2
193	Declared RISCOP.RESET to be volatile so that -O2 optimization would not optimize away the correct behavior by trying to be too clever.	chris	8346d 16h	/or1k/tags/stable_0_2_0_rc2
192	Removed GlobalMode reference causing problems for --disable-debugmod option.	chris	8347d 01h	/or1k/tags/stable_0_2_0_rc2
191	Added UART jitter var to sim config	chris	8347d 21h	/or1k/tags/stable_0_2_0_rc2
190	Added jitter initialization	chris	8347d 21h	/or1k/tags/stable_0_2_0_rc2
189	fixed mode handling for tick facility	chris	8347d 21h	/or1k/tags/stable_0_2_0_rc2
188	fixed PIC interrupt controller	chris	8347d 21h	/or1k/tags/stable_0_2_0_rc2
187	minor change to clear pending exception	chris	8347d 21h	/or1k/tags/stable_0_2_0_rc2
186	major change to UART structure	chris	8347d 21h	/or1k/tags/stable_0_2_0_rc2