URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc2] - Rev 219

Rev	Log message	Author	Age	Path
199	Initial import	simons	8343d 22h	/or1k/tags/stable_0_2_0_rc2
198	Moved from testbench.old	simons	8346d 09h	/or1k/tags/stable_0_2_0_rc2
197	This is not used any more.	simons	8346d 09h	/or1k/tags/stable_0_2_0_rc2
196	Configuration SPRs added.	simons	8346d 10h	/or1k/tags/stable_0_2_0_rc2
195	New test added.	simons	8346d 10h	/or1k/tags/stable_0_2_0_rc2
194	Fixed a bug for little endian architectures. Could cause a hang of gdb under some circumstances.	chris	8346d 18h	/or1k/tags/stable_0_2_0_rc2
193	Declared RISCOP.RESET to be volatile so that -O2 optimization would not optimize away the correct behavior by trying to be too clever.	chris	8346d 18h	/or1k/tags/stable_0_2_0_rc2
192	Removed GlobalMode reference causing problems for --disable-debugmod option.	chris	8347d 03h	/or1k/tags/stable_0_2_0_rc2
191	Added UART jitter var to sim config	chris	8348d 00h	/or1k/tags/stable_0_2_0_rc2
190	Added jitter initialization	chris	8348d 00h	/or1k/tags/stable_0_2_0_rc2