URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [asyst_2/] [rtl/] [verilog/] - Rev 113

Rev	Log message	Author	Age	Path
66	Changed empty status generation in pciw_fifo_control.v	mihad	7942d 10h	/pci/tags/asyst_2/rtl/verilog
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7945d 08h	/pci/tags/asyst_2/rtl/verilog
63	Added additional testcase and changed rst name in BIST to trst	mihad	7945d 12h	/pci/tags/asyst_2/rtl/verilog
62	Added BIST signals for RAMs.	mihad	7948d 05h	/pci/tags/asyst_2/rtl/verilog
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7956d 05h	/pci/tags/asyst_2/rtl/verilog
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7956d 06h	/pci/tags/asyst_2/rtl/verilog
58	Removed all logic from asynchronous reset network	mihad	7961d 06h	/pci/tags/asyst_2/rtl/verilog
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7961d 12h	/pci/tags/asyst_2/rtl/verilog
56	Number of state bits define was removed	mihad	7962d 03h	/pci/tags/asyst_2/rtl/verilog
55	Changed state machine encoding to true one-hot	mihad	7962d 04h	/pci/tags/asyst_2/rtl/verilog