URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [asyst_2/] [rtl/] [verilog/] - Rev 154

Rev	Log message	Author	Age	Path
86	Entered the option to disable no response counter in wb master.	mihad	7775d 17h	/pci/tags/asyst_2/rtl/verilog
83	Cleaned up the code. No functional changes.	mihad	7804d 14h	/pci/tags/asyst_2/rtl/verilog
81	Updated synchronization in top level fifo modules.	mihad	7818d 10h	/pci/tags/asyst_2/rtl/verilog
79	Updated.	mihad	7821d 15h	/pci/tags/asyst_2/rtl/verilog
78	Old files with wrong names removed.	mihad	7821d 15h	/pci/tags/asyst_2/rtl/verilog
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7821d 15h	/pci/tags/asyst_2/rtl/verilog
73	Bug fixes, testcases added.	mihad	7827d 16h	/pci/tags/asyst_2/rtl/verilog
72	* empty log message *	mihad	7874d 20h	/pci/tags/asyst_2/rtl/verilog
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7882d 12h	/pci/tags/asyst_2/rtl/verilog
69	Changed BIST signal names etc..	mihad	7919d 19h	/pci/tags/asyst_2/rtl/verilog