URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [asyst_2/] [rtl/] [verilog] - Rev 116

Rev	Log message	Author	Age	Path
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	8002d 05h	/pci/tags/asyst_2/rtl/verilog
67	Changed BIST signals for RAMs.	tadejm	8002d 10h	/pci/tags/asyst_2/rtl/verilog
66	Changed empty status generation in pciw_fifo_control.v	mihad	8005d 20h	/pci/tags/asyst_2/rtl/verilog
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	8008d 18h	/pci/tags/asyst_2/rtl/verilog
63	Added additional testcase and changed rst name in BIST to trst	mihad	8008d 22h	/pci/tags/asyst_2/rtl/verilog
62	Added BIST signals for RAMs.	mihad	8011d 15h	/pci/tags/asyst_2/rtl/verilog
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	8019d 15h	/pci/tags/asyst_2/rtl/verilog
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	8019d 16h	/pci/tags/asyst_2/rtl/verilog
58	Removed all logic from asynchronous reset network	mihad	8024d 17h	/pci/tags/asyst_2/rtl/verilog
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	8024d 23h	/pci/tags/asyst_2/rtl/verilog