URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [asyst_2/] [rtl/] [verilog] - Rev 124

Rev	Log message	Author	Age	Path
72	* empty log message *	mihad	7895d 01h	/pci/tags/asyst_2/rtl/verilog
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7902d 17h	/pci/tags/asyst_2/rtl/verilog
69	Changed BIST signal names etc..	mihad	7940d 01h	/pci/tags/asyst_2/rtl/verilog
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7943d 10h	/pci/tags/asyst_2/rtl/verilog
67	Changed BIST signals for RAMs.	tadejm	7943d 15h	/pci/tags/asyst_2/rtl/verilog
66	Changed empty status generation in pciw_fifo_control.v	mihad	7947d 01h	/pci/tags/asyst_2/rtl/verilog
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7949d 23h	/pci/tags/asyst_2/rtl/verilog
63	Added additional testcase and changed rst name in BIST to trst	mihad	7950d 03h	/pci/tags/asyst_2/rtl/verilog
62	Added BIST signals for RAMs.	mihad	7952d 20h	/pci/tags/asyst_2/rtl/verilog
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7960d 20h	/pci/tags/asyst_2/rtl/verilog