URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [asyst_3] - Rev 92

Rev	Log message	Author	Age	Path
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	8006d 10h	/pci/tags/asyst_3
67	Changed BIST signals for RAMs.	tadejm	8006d 15h	/pci/tags/asyst_3
66	Changed empty status generation in pciw_fifo_control.v	mihad	8010d 01h	/pci/tags/asyst_3
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	8013d 00h	/pci/tags/asyst_3
64	The testcase I just added in previous revision repaired	mihad	8013d 02h	/pci/tags/asyst_3
63	Added additional testcase and changed rst name in BIST to trst	mihad	8013d 04h	/pci/tags/asyst_3
62	Added BIST signals for RAMs.	mihad	8015d 21h	/pci/tags/asyst_3
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	8023d 20h	/pci/tags/asyst_3
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	8023d 22h	/pci/tags/asyst_3
58	Removed all logic from asynchronous reset network	mihad	8028d 22h	/pci/tags/asyst_3