URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_10] - Rev 83

Rev	Log message	Author	Age	Path
58	Removed all logic from asynchronous reset network	mihad	7964d 23h	/pci/tags/rel_10
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7965d 05h	/pci/tags/rel_10
56	Number of state bits define was removed	mihad	7965d 20h	/pci/tags/rel_10
55	Changed state machine encoding to true one-hot	mihad	7965d 21h	/pci/tags/rel_10
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	7998d 22h	/pci/tags/rel_10
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7999d 02h	/pci/tags/rel_10
52	Oops, never before noticed that OC header is missing	mihad	7999d 06h	/pci/tags/rel_10
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7999d 06h	/pci/tags/rel_10
50	Got rid of undef directives	mihad	8001d 22h	/pci/tags/rel_10
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	8001d 22h	/pci/tags/rel_10