URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_7/] - Rev 91

Rev	Log message	Author	Age	Path
67	Changed BIST signals for RAMs.	tadejm	7957d 23h	/pci/tags/rel_7
66	Changed empty status generation in pciw_fifo_control.v	mihad	7961d 10h	/pci/tags/rel_7
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7964d 08h	/pci/tags/rel_7
64	The testcase I just added in previous revision repaired	mihad	7964d 10h	/pci/tags/rel_7
63	Added additional testcase and changed rst name in BIST to trst	mihad	7964d 12h	/pci/tags/rel_7
62	Added BIST signals for RAMs.	mihad	7967d 05h	/pci/tags/rel_7
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7975d 05h	/pci/tags/rel_7
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7975d 06h	/pci/tags/rel_7
58	Removed all logic from asynchronous reset network	mihad	7980d 06h	/pci/tags/rel_7
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7980d 12h	/pci/tags/rel_7