URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_7/] [rtl/] - Rev 114

Rev	Log message	Author	Age	Path
67	Changed BIST signals for RAMs.	tadejm	8000d 15h	/pci/tags/rel_7/rtl
66	Changed empty status generation in pciw_fifo_control.v	mihad	8004d 01h	/pci/tags/rel_7/rtl
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	8006d 23h	/pci/tags/rel_7/rtl
63	Added additional testcase and changed rst name in BIST to trst	mihad	8007d 03h	/pci/tags/rel_7/rtl
62	Added BIST signals for RAMs.	mihad	8009d 20h	/pci/tags/rel_7/rtl
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	8017d 20h	/pci/tags/rel_7/rtl
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	8017d 21h	/pci/tags/rel_7/rtl
58	Removed all logic from asynchronous reset network	mihad	8022d 21h	/pci/tags/rel_7/rtl
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	8023d 03h	/pci/tags/rel_7/rtl
56	Number of state bits define was removed	mihad	8023d 18h	/pci/tags/rel_7/rtl