URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_7/] [rtl/] [verilog/] - Rev 154

Rev	Log message	Author	Age	Path
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7955d 16h	/pci/tags/rel_7/rtl/verilog
67	Changed BIST signals for RAMs.	tadejm	7955d 21h	/pci/tags/rel_7/rtl/verilog
66	Changed empty status generation in pciw_fifo_control.v	mihad	7959d 07h	/pci/tags/rel_7/rtl/verilog
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7962d 05h	/pci/tags/rel_7/rtl/verilog
63	Added additional testcase and changed rst name in BIST to trst	mihad	7962d 09h	/pci/tags/rel_7/rtl/verilog
62	Added BIST signals for RAMs.	mihad	7965d 02h	/pci/tags/rel_7/rtl/verilog
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7973d 02h	/pci/tags/rel_7/rtl/verilog
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7973d 03h	/pci/tags/rel_7/rtl/verilog
58	Removed all logic from asynchronous reset network	mihad	7978d 03h	/pci/tags/rel_7/rtl/verilog
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7978d 09h	/pci/tags/rel_7/rtl/verilog