URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_8/] [rtl] - Rev 110

Rev	Log message	Author	Age	Path
63	Added additional testcase and changed rst name in BIST to trst	mihad	7974d 11h	/pci/tags/rel_8/rtl
62	Added BIST signals for RAMs.	mihad	7977d 04h	/pci/tags/rel_8/rtl
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7985d 04h	/pci/tags/rel_8/rtl
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7985d 05h	/pci/tags/rel_8/rtl
58	Removed all logic from asynchronous reset network	mihad	7990d 05h	/pci/tags/rel_8/rtl
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7990d 11h	/pci/tags/rel_8/rtl
56	Number of state bits define was removed	mihad	7991d 02h	/pci/tags/rel_8/rtl
55	Changed state machine encoding to true one-hot	mihad	7991d 03h	/pci/tags/rel_8/rtl
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	8024d 08h	/pci/tags/rel_8/rtl
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	8024d 12h	/pci/tags/rel_8/rtl