URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_8/] [rtl] - Rev 115

Rev	Log message	Author	Age	Path
67	Changed BIST signals for RAMs.	tadejm	7973d 19h	/pci/tags/rel_8/rtl
66	Changed empty status generation in pciw_fifo_control.v	mihad	7977d 05h	/pci/tags/rel_8/rtl
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7980d 03h	/pci/tags/rel_8/rtl
63	Added additional testcase and changed rst name in BIST to trst	mihad	7980d 07h	/pci/tags/rel_8/rtl
62	Added BIST signals for RAMs.	mihad	7983d 00h	/pci/tags/rel_8/rtl
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7991d 00h	/pci/tags/rel_8/rtl
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7991d 01h	/pci/tags/rel_8/rtl
58	Removed all logic from asynchronous reset network	mihad	7996d 02h	/pci/tags/rel_8/rtl
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7996d 08h	/pci/tags/rel_8/rtl
56	Number of state bits define was removed	mihad	7996d 22h	/pci/tags/rel_8/rtl