URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_8/] [rtl] - Rev 154

Rev	Log message	Author	Age	Path
72	* empty log message *	mihad	7988d 23h	/pci/tags/rel_8/rtl
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7996d 15h	/pci/tags/rel_8/rtl
69	Changed BIST signal names etc..	mihad	8033d 23h	/pci/tags/rel_8/rtl
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	8037d 08h	/pci/tags/rel_8/rtl
67	Changed BIST signals for RAMs.	tadejm	8037d 13h	/pci/tags/rel_8/rtl
66	Changed empty status generation in pciw_fifo_control.v	mihad	8040d 23h	/pci/tags/rel_8/rtl
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	8043d 21h	/pci/tags/rel_8/rtl
63	Added additional testcase and changed rst name in BIST to trst	mihad	8044d 02h	/pci/tags/rel_8/rtl
62	Added BIST signals for RAMs.	mihad	8046d 18h	/pci/tags/rel_8/rtl
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	8054d 18h	/pci/tags/rel_8/rtl