URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

Subversion Repositories s1_core

[/] [s1_core/] [trunk] - Rev 72

Rev	Log message	Author	Age	Path
52	Updated SPARC Core files from OpenSPARC T1 version 1.4 to version 1.5	fafa1971	6185d 01h	/s1_core/trunk
51	User Chris "gaterocket" corrected a couple of errors for FPGA boards: blocking assignments and two uninitialized variables.	fafa1971	6271d 01h	/s1_core/trunk
50	Changed library paths for XST from macrocell to behav.	fafa1971	6287d 08h	/s1_core/trunk
49	Now supports 3 versions: S1 Core ME/SE/EE.	fafa1971	6294d 09h	/s1_core/trunk
48	Updated with new OpenSPARC 1.4 list	fafa1971	6335d 23h	/s1_core/trunk
47	Updated with `define preprocessing for Xilinx XST synthesis	fafa1971	6335d 23h	/s1_core/trunk
46	Fresh version from OpenSPARC 1.4 and Icarus define preprocessing	fafa1971	6335d 23h	/s1_core/trunk
45	I'm going to remove original OpenSPARC 1.4 files so that I can insert again the ones with Icarus Verilog preprocessor already applied by update_sparccore (it seems that Xilinx's XST does NOT support defines at compile time)	fafa1971	6336d 00h	/s1_core/trunk
44	Embedded `defines into Verilog source since did not find command line option for XST	fafa1971	6336d 22h	/s1_core/trunk
43	Added welcome message as a remainder to set paths for tools!=IVerilog	fafa1971	6336d 22h	/s1_core/trunk