URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] - Rev 29

Rev	Log message	Author	Age	Path
9	SDR Bus width parameter passing issue across the models are fixed	dinesha	4520d 21h	/sdr_ctrl
8	test bench files are added into SVN	dinesha	4520d 21h	/sdr_ctrl
7	SDRAM Memory Models are added into SVN	dinesha	4520d 21h	/sdr_ctrl
6	Golden Log files are added into SVN	dinesha	4520d 21h	/sdr_ctrl
5	Run files are updated into SVN	dinesha	4520d 21h	/sdr_ctrl
4	Sdram controller RTL bug fixes done for 16bit SDR Mode	dinesha	4521d 18h	/sdr_ctrl
3	SDRAM controller core files are checked in	dinesha	4528d 04h	/sdr_ctrl
2		dinesha	4530d 20h	/sdr_ctrl
1	The project and the structure was created	root	4534d 20h	/sdr_ctrl