URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl] - Rev 61

Rev	Log message	Author	Age	Path
41	Updated Spec ver 0.1 is added back to svn	dinesha	4516d 14h	/sdr_ctrl
40	Application layer Fifo full conditional are register now to synth timing fixes	dinesha	4517d 07h	/sdr_ctrl
39	Test Bench upgradation with bigger data burst size	dinesha	4517d 07h	/sdr_ctrl
38	Port Name clean up	dinesha	4518d 12h	/sdr_ctrl
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4518d 14h	/sdr_ctrl
36	Clean up	dinesha	4519d 05h	/sdr_ctrl
35	Updated the New Documents - ver 0.1	dinesha	4519d 06h	/sdr_ctrl
34	Removed the older version	dinesha	4519d 07h	/sdr_ctrl
33	clean up	dinesha	4519d 07h	/sdr_ctrl
32	Debug is enable through +define	dinesha	4521d 06h	/sdr_ctrl