URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl] - Rev 69

Rev	Log message	Author	Age	Path
49	clean up	dinesha	4501d 00h	/sdr_ctrl
48	top-level cleanup	dinesha	4501d 00h	/sdr_ctrl
47	SDRAM bus converter bug fix and top-level signal clean up	dinesha	4501d 00h	/sdr_ctrl
46	test bench upgrade + rtl cleanup	dinesha	4503d 01h	/sdr_ctrl
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4503d 05h	/sdr_ctrl
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	4505d 03h	/sdr_ctrl
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	4505d 05h	/sdr_ctrl
42	Bug fix in read access is fixed	dinesha	4505d 05h	/sdr_ctrl
41	Updated Spec ver 0.1 is added back to svn	dinesha	4505d 07h	/sdr_ctrl
40	Application layer Fifo full conditional are register now to synth timing fixes	dinesha	4505d 23h	/sdr_ctrl