URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [sys] - Rev 135

Rev	Log message	Author	Age	Path
101	Added new designs for minsoc release candidate convert tool set to parse proper ip-xact THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT	jt_eaton	4596d 05h	/socgen/trunk/tools/sys
100	created workspace prroject=fpga_mrisc for single compile general cleanup	jt_eaton	4608d 12h	/socgen/trunk/tools/sys
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4651d 05h	/socgen/trunk/tools/sys
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4687d 10h	/socgen/trunk/tools/sys
96	hierConnections now create ports	jt_eaton	4761d 06h	/socgen/trunk/tools/sys
95	added first cut at busdefs added clock reset enable pads and jtag_rpc	jt_eaton	4770d 04h	/socgen/trunk/tools/sys
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4797d 05h	/socgen/trunk/tools/sys
93	build scripts now support model views linting and coverage starting to work again	jt_eaton	4809d 18h	/socgen/trunk/tools/sys
92	all testbenchs now built from /sim/xml files bench /models now in Testbench	jt_eaton	4814d 19h	/socgen/trunk/tools/sys
90	now build all testbenches from ip-xact files and list as testbench in design.soc	jt_eaton	4823d 05h	/socgen/trunk/tools/sys