OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_beta/] - Rev 294

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
175 add bug report
"MSB of Program Counter changed upon PC increment"		 arniml 6971d 17h /t48/tags/rel_0_6_beta
174 fix bug report
"MSB of Program Counter changed upon PC increment"		 arniml 6971d 17h /t48/tags/rel_0_6_beta
173 testcase for bug report
"MSB of Program Counter changed upon PC increment"		 arniml 6971d 17h /t48/tags/rel_0_6_beta
172 save data from wishbone bus in register bank with wb_ack
necessary to hold data from peripheral/memory until it is read by T48		 arniml 7000d 13h /t48/tags/rel_0_6_beta
171 remove obsolete output stack_high_o arniml 7001d 13h /t48/tags/rel_0_6_beta
170 intermediate update arniml 7002d 20h /t48/tags/rel_0_6_beta
169 initial check-in arniml 7003d 01h /t48/tags/rel_0_6_beta
168 change address range of wb_master arniml 7003d 01h /t48/tags/rel_0_6_beta
167 simplify address range:
- configuration range
- Wishbone range		 arniml 7003d 01h /t48/tags/rel_0_6_beta
166 assign default for state_s arniml 7004d 17h /t48/tags/rel_0_6_beta

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.