OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_1] - Rev 142

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
122 test MB after return from interrupt arniml 7316d 07h /t48/tags/rel_1_1
121 update bug description for
Program Memory bank can be switched during interrupt
arniml 7319d 01h /t48/tags/rel_1_1
120 Fix bug report:
"Program Memory bank can be switched during interrupt"
int module emits int_in_progress signal that is used inside the decoder
to hold mb low for JMP and CALL during interrupts
arniml 7319d 01h /t48/tags/rel_1_1
119 add int_in_progress_o to entity of int module arniml 7319d 01h /t48/tags/rel_1_1
118 test MB/interrupt behaviour according to bug report
"Program Memory bank can be switched during interrupt"
arniml 7319d 01h /t48/tags/rel_1_1
117 add bug
Program Memory bank can be switched during interrupt
arniml 7320d 01h /t48/tags/rel_1_1
116 adapt to GHDL 0.12 / gcc 3.4.0 arniml 7348d 01h /t48/tags/rel_1_1
115 extend description arniml 7349d 06h /t48/tags/rel_1_1
114 initial check-in arniml 7353d 01h /t48/tags/rel_1_1
113 generate two ROM files based on address:
+ 0 - 2047 : 2k internal ROM
+ 2048 - 4095 : 2k external ROM
arniml 7359d 11h /t48/tags/rel_1_1

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.