OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_1] - Rev 79

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
59 increment prescaler with MSTATE4 arniml 7395d 23h /t48/tags/rel_1_1
58 add periodic interrupt arniml 7395d 23h /t48/tags/rel_1_1
57 abort if no interrupt occurs arniml 7395d 23h /t48/tags/rel_1_1
56 wait for instruction strobe after final end-of-simulation detection
this ensures that the last mov instruction is part of the dump and
enables 100% matching with i8039 simulator
arniml 7397d 00h /t48/tags/rel_1_1
55 add dependency to tb_behav_pack for decoder arniml 7397d 00h /t48/tags/rel_1_1
54 - add tb_istrobe_s arniml 7397d 00h /t48/tags/rel_1_1
53 make istrobe visible through testbench package arniml 7397d 00h /t48/tags/rel_1_1
52 + fix bug in PSW[3]
+ read SP properly for dump
arniml 7397d 00h /t48/tags/rel_1_1
51 + implement Port1 and Port2
+ connect T0 and T1
+ return proper program memory contents
arniml 7397d 00h /t48/tags/rel_1_1
49 Imported sources arniml 7402d 02h /t48/tags/rel_1_1

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.