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[/] [t48/] [tags/] [rel_1_4/] - Rev 123

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103 add testbench peripherals for P1 and P2
this became necessary to observe a difference between externally applied
port data and internally applied port data		 arniml 7362d 01h /t48/tags/rel_1_4
102 update for changes in address space of external memory arniml 7362d 01h /t48/tags/rel_1_4
101 assert p2_read_p2_o when expander port is read arniml 7362d 01h /t48/tags/rel_1_4
100 reorder data_o generation arniml 7362d 02h /t48/tags/rel_1_4
99 initial check-in arniml 7362d 02h /t48/tags/rel_1_4
98 Fix bug "ANL and ORL to P1/P2 read port status instead of port output register" arniml 7362d 02h /t48/tags/rel_1_4
97 initial check-in arniml 7362d 02h /t48/tags/rel_1_4
96 select dedicated directorie(s) for regression arniml 7363d 00h /t48/tags/rel_1_4
95 check counter inactivity arniml 7363d 00h /t48/tags/rel_1_4
94 initial check-in arniml 7363d 00h /t48/tags/rel_1_4

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