URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_4] - Rev 173

Rev	Log message	Author	Age	Path
153	introduced generic gate_port_input_g forces masking of P1 and P2 input bus	arniml	7163d 15h	/t48/tags/rel_1_4
152	added hierarchy t8048_notri and system components package	arniml	7164d 06h	/t48/tags/rel_1_4
151	added hierarchy t8048_notri and components package for t48 systems	arniml	7164d 06h	/t48/tags/rel_1_4
150	intruduced hierarchy t8048_notri where all system functionality except bidirectional ports is handled	arniml	7164d 14h	/t48/tags/rel_1_4
149	update	arniml	7164d 14h	/t48/tags/rel_1_4
148	initial check-in	arniml	7164d 14h	/t48/tags/rel_1_4
147	initial check-in for release 0.5 BETA	arniml	7200d 16h	/t48/tags/rel_1_4
146	add bug RD' and WR' not asserted for INS A, BUS and OUTL BUS, A	arniml	7201d 16h	/t48/tags/rel_1_4
145	remove PROG and end of XTAL2, see comment for details	arniml	7201d 17h	/t48/tags/rel_1_4
144	delay db_dir_o by one machine cycle this fixes the timing relation between BUS data and WR'	arniml	7201d 17h	/t48/tags/rel_1_4