URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_4] - Rev 192

Rev	Log message	Author	Age	Path
172	save data from wishbone bus in register bank with wb_ack necessary to hold data from peripheral/memory until it is read by T48	arniml	7033d 03h	/t48/tags/rel_1_4
171	remove obsolete output stack_high_o	arniml	7034d 03h	/t48/tags/rel_1_4
170	intermediate update	arniml	7035d 10h	/t48/tags/rel_1_4
169	initial check-in	arniml	7035d 15h	/t48/tags/rel_1_4
168	change address range of wb_master	arniml	7035d 15h	/t48/tags/rel_1_4
167	simplify address range: - configuration range - Wishbone range	arniml	7035d 15h	/t48/tags/rel_1_4
166	assign default for state_s	arniml	7037d 07h	/t48/tags/rel_1_4
165	add component wb_master.vhd	arniml	7038d 06h	/t48/tags/rel_1_4
164	initial check-in	arniml	7038d 06h	/t48/tags/rel_1_4
163	add bug Wrong clock applied to T0	arniml	7039d 05h	/t48/tags/rel_1_4