URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm.v] - Rev 111

Rev	Log message	Author	Age	Path
77	ZPG coded. Simulation is halfway.	creep	5622d 13h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
71	Four addressing modes are simulated: immediate, accumulator, implied and absolute. The simulation was done using a testbench that contains a small memory inside.	creep	5622d 14h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
70	Fixed several timing. Registered outputs working. Only three adressing modes coded, the previous coding was erased.	creep	5626d 10h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
68	The FSM module is now parametrized. Also, several changes were made to remove most of the lint warnings.	creep	5626d 13h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
63	Fixed several HAL warnings. Still plenty to do.	creep	5627d 10h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
61	File name change to lowercase. HAL says so!	creep	5627d 10h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v