URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm.v] - Rev 186

Rev	Log message	Author	Age	Path
88	Absolute indexed mode, READ TYPE instruction when page IS crossed is coded and simulated.	creep	5599d 15h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
87	Absolute indexed mode, READ TYPE instruction when no page is crossed is coded and simulated.	creep	5600d 06h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
86	Zero page indexed mode is working fine.	creep	5600d 10h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
83	Completed HAL checking. All the relevant warnings and errors were removed.	creep	5600d 15h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
82	Did some checking with HAL and fixed 20+ warnings and errors.	creep	5601d 07h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
78	ZPG coded and simulated.	creep	5601d 09h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
77	ZPG coded. Simulation is halfway.	creep	5601d 10h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
71	Four addressing modes are simulated: immediate, accumulator, implied and absolute. The simulation was done using a testbench that contains a small memory inside.	creep	5601d 10h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
70	Fixed several timing. Registered outputs working. Only three adressing modes coded, the previous coding was erased.	creep	5605d 07h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
68	The FSM module is now parametrized. Also, several changes were made to remove most of the lint warnings.	creep	5605d 09h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v