URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm.v] - Rev 196

Rev	Log message	Author	Age	Path
96	IDY READ TYPE instructions are coded and simulated. IDY WRITE TYPE instructions are coded but still requires simulation.	creep	5619d 11h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
95	IDX addressing mode is also 100%, coded and simulated.	creep	5619d 14h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
94	Relative addressing mode is almost 100% functional. It just needs another test to check if the adrres_plus_index logic is not recalculating the pc in two consecutive cycles.	creep	5620d 11h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
88	Absolute indexed mode, READ TYPE instruction when page IS crossed is coded and simulated.	creep	5620d 19h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
87	Absolute indexed mode, READ TYPE instruction when no page is crossed is coded and simulated.	creep	5621d 10h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
86	Zero page indexed mode is working fine.	creep	5621d 14h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
83	Completed HAL checking. All the relevant warnings and errors were removed.	creep	5621d 19h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
82	Did some checking with HAL and fixed 20+ warnings and errors.	creep	5622d 11h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
78	ZPG coded and simulated.	creep	5622d 13h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
77	ZPG coded. Simulation is halfway.	creep	5622d 14h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v