URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm.v] - Rev 255

Rev	Log message	Author	Age	Path
110	All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage.	creep	5588d 04h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
109	PLA and PLP are coded and simulated.	creep	5588d 07h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
108	PHA and PHP are coded and simulated.	creep	5588d 08h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
107	The RTS instruction is working fine. Coded and simulated.	creep	5588d 09h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
105	The RTI instruction is working fine. Coded and simulated.	creep	5588d 09h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
104	The BRK instruction is working. The reset vector was tested also.	creep	5588d 11h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
103	Some early modifications to support the special stack instructions.	creep	5589d 05h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
102	Some early modifications to support the special stack instructions.	creep	5589d 07h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
101	Absolute indirect addressing mode is coded and simulated.	creep	5589d 11h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
100	IDY WRITE TYPE instructions are coded and simulated.	creep	5589d 12h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm.v