URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm_tb.v] - Rev 246

Rev	Log message	Author	Age	Path
92	Absolute indexed mode working properly. All cases were simulated.	creep	5569d 21h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
91	Absolute indexed mode, READ_MODIFY_WRITE TYPE instruction when page IS crossed is coded and simulated.	creep	5569d 21h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
89	Absolute indexed mode, READ_MODIFY_WRITE TYPE instruction when page is NOT crossed is coded and simulated.	creep	5569d 22h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
88	Absolute indexed mode, READ TYPE instruction when page IS crossed is coded and simulated.	creep	5569d 22h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
87	Absolute indexed mode, READ TYPE instruction when no page is crossed is coded and simulated.	creep	5570d 14h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
86	Zero page indexed mode is working fine.	creep	5570d 17h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
78	ZPG coded and simulated.	creep	5571d 16h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
76	ABS write instructions were not simulated. Also added some initial ZPG simulation.	creep	5571d 17h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
71	Four addressing modes are simulated: immediate, accumulator, implied and absolute. The simulation was done using a testbench that contains a small memory inside.	creep	5571d 18h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
68	The FSM module is now parametrized. Also, several changes were made to remove most of the lint warnings.	creep	5575d 17h	/t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v